Technical Field
The present invention generally relates to semiconductor layouts, and more particularly to devices and methods for laying out vertical transistor designs with merged active areas (e.g., bottom source and drain regions) to reduce resistance and improve layout area.
Description of the Related Art
Vertical field-effect transistors (VFETs) include a channel perpendicular to a surface of a substrate on which the VFET is formed, as opposed to being situated along a plane of the surface of the substrate. This increases the packing density of these devices and improves a scaling limit beyond planar finFETs.
However, vertical FETs are challenged by the separate nature of the devices. The devices or even groups of devices are separated from each other across isolation boundaries, well boundaries and region boundaries. Small narrow active area (RX) regions can result in higher resistance to power supplies due to normal critical dimension (CD) and overlay variation (e.g., between lithographic masks, etc.). As a result, power supply connections and device structures that need to adapt to these conditions consume precious real estate on the substrate.
Therefore, a need exists for circuit layouts for VFETs that reduce the burden on power supplies and preserve layout area.